According to the protocols of the Federal Communication Commission (FCC) and the International Electrotechnical Commission (IEC), the power of electromagnetic interference (EMI) needs to be confined within a regulatory limit. Consequently, a synchronous digital system is usually equipped with a spread spectrum clock generator (SSCG) to reduce the spectral density of electromagnetic interference. For example, the synchronous digital system is a transceiver for a PCIe bus, a SATA bus or a SAS bus.
FIG. 1 is a schematic circuit block diagram illustrating a conventional multi-channel transceiver. As shown in FIG. 1, the multi-channel transceiver 100 comprises a spread spectrum clock generator 120 and M serializers/deserializers (also referred as Ser/Des) 111˜11m. The channel corresponding to each of the serializers/deserializers 111˜11m may perform the conversion between parallel data and serial data.
Take the channel corresponding to the serializer/deserializer 111 and a first input/output port I/O1 for example. The serializer/deserializer 111 may receive a first parallel data PDATA1 and convert the first parallel data PDATA1 into a first serial data SDATA1 according to a spread spectrum clock signal SSCLK. Consequently, the first serial data SDATA1 is outputted from the first input/output port I/O1. Similarly, the serializer/deserializer 111 may receive the first serial data SDATA1 from the first input/output port I/O1 and convert the first serial data SDATA1 into the first parallel data PDATA1 according to the spread spectrum clock signal SSCLK.
The conventional multi-channel transceiver 100 is only equipped with one spread spectrum clock generator 120 to generate the spread spectrum clock signal SSCLK and transmit the spread spectrum clock signal SSCLK to all of the serializers/deserializers 111˜11m. Consequently, the conversions between the parallel data PDATA1˜PDATAm and the serial data SDATA1˜SDATAm are performed by the serializers/deserializers 111˜11m according to the spread spectrum clock signal SSCLK.
Generally, the spread spectrum clock generator 120 comprises a phase-locked loop circuit (PLL) and a delta-sigma modulation circuit so as to generate the spread spectrum clock signal SSCLK with a spread spectrum clocking frequency deviation. In other words, the spread spectrum clock generator 120 may generate various SSCG profiles according to the spread spectrum clocking frequency deviations of different specifications.
For example, in case that the data rate for a SATA bus is 1.5 Gbps, the spread spectrum clocking frequency deviation is down spread to −5000 ppm. Consequently, the frequency of the spread spectrum clock signal SSCLK is in the range between 1.5 GHz˜1.425 GHz, which is the SSCG profile of the spread spectrum clock signal SSCLK at 1.5 GHz. Whereas, in case that the data rate for a SATA bus is 6 Gbps, the spread spectrum clocking frequency deviation is center spread from +2300 ppm to −2300 ppm. Consequently, the frequency of the spread spectrum clock signal SSCLK is in the range between the 6.138 GHz and 5.862 GHz, which is the SSCG profile of the spread spectrum clock signal SSCLK at 6 GHz.
According to the specifications, all channels of the multi-channel transceiver 100 need to use different SSCG profiles to support different data rates. For example, the data rates for the SATA bus may be 1.5 Gbps, 3 Gbps, 6 Gbps and 12 Gbps and varied according to different spread spectrum clocking frequency deviations. However, since the conventional multi-channel transceiver 100 is only equipped with one spread spectrum clock generator 120, the generated spread spectrum clock signal SSCLK only has a single SSCG profile. In other words, all channels of the conventional multi-channel transceiver 100 cannot provide various SSCG profiles to support different data rates.
Moreover, the serializers/deserializers 111˜11m generate sampling clocks according to the spread spectrum clock signal SSCLK, and samples the received serial data SDATA1˜SDATAm according to the sampling clocks. However, since the spread spectrum clock signal SSCLK is generated by the spread spectrum clock generator 120, the sampling clocks also have the clocking frequency deviations. Due to the clocking frequency deviations of the sampling clocks, the sampling time margin is reduced and the performance of the multi-channel transceiver 100 is impaired.